Optimizing Bus Line Based on Metro-Bus Integration

Fairness in optimizing bus-crew scheduling process

This work proposes a model considering fairness in the problem of crew scheduling for bus drivers (CSP-BD) using a hybrid ant-colony optimization (HACO) algorithm to solve it. The main contributions of this work are the following: (a) a valid approach for cases with a special cost structure and constraints considering the fairness of working time and idle time; (b) an improved algorithm incorpo...

Couplers Upper Bus Lower Bus

Bus-Based COMA - Reducing Traffic in Shared-Bus Multiprocessors

A problem with bus-based shared-memory multiprocessors is that the shared bus rapidly becomes a bottleneck in the machine, effectively limiting the machine size to somewhere between ten and twenty processors. We propose a new architecture, the Bus-Based COMA (BB-COMA) that addresses this problem. Compared to the standard UMA architecture, the BB-COMA has lower requirements on bus bandwidth. We ...

Global Bus Design of a Bus-Based COMA Multiprocessor DICE

DICE is a shared-bus multiprocessor based on a distributed shared-memory architecture, known as Cache-Only Memory Architecture (COMA). Unlike previous COMA proposals for large-scale multiprocessing, DICE utilizes the COMA to effectively decrease the gap between modern high-performance microprocessors and the bus. As microprocessors become faster and demand more bandwidth, the already limited sc...

Tool Integration with the Evidential Tool Bus

Formal and semi-formal tools are now being used in large projects both for development and certification. A typical project integrates many diverse tools such as static analyzers, model checkers, test generators, and constraint solvers. These tools are usually integrated in an ad hoc manner. There is, however, a need for a tool integration framework that can be used to systematically create wor...